AI FOR EDA · FALL 2027
I am Zeen Fang, a microelectronics undergraduate at Central South University. I build device and circuit models, connect simulation tools with Codex, and check the results against physical assumptions and controlled comparisons.
I am seeking PhD opportunities for Fall 2027 in AI for EDA, chip design space exploration, and hardware design verification.
RESEARCH PRACTICE
My current training is in microelectronics and device and circuit modelling. I use Codex to assist with simulation setup, parameter sweeps, data organisation and manuscript preparation in TCAD, Cadence Virtuoso and PSpice. I check the results against physical assumptions and the original outputs.
Documented research practice
Codex helps configure Silvaco ATLAS experiments, organise parameter sweeps, parse logs and prepare figures. I check physical assumptions, solver behaviour and the limits of the extracted metrics.
Read the TCAD workflowTeam design and simulation
I use Codex to help organise circuit simulation tasks and analyse outputs. The team LDO project provides experience with PVT, PSRR, stability, physical verification and post-layout evaluation.
View the LDO caseOngoing research · manuscript in preparation
For my second-order memristor work, I use Codex in model setup, simulation runs, data extraction and manuscript preparation. Matched-state and history-off comparisons help separate the effects of internal states.
See the current modelEach environment retains its own solver. I define the research question and comparison conditions, review the raw outputs, and decide which conclusions the evidence supports.
I constrained a Codex harness around local Silvaco ATLAS to turn paper reading, parameterized device sweeps, log parsing, figure generation, and scientific stop rules into one traceable research-training loop.
Codex supported workspace inspection, experiment matrices, parsing, and audits; ATLAS remained the solver, while I owned the physical assumptions, run authorization, stopping rules, and claim promotion.
PROPOSED RESEARCH
I would like to build on my device and circuit modelling experience while learning the computing foundations for AI for EDA. These are proposed research directions that I hope to explore with guidance and further study.
AI for EDA
My experience so far is in using Codex to assist device and circuit simulations. I would like to learn how AI can support more of the EDA workflow, starting with small tasks whose outputs I can inspect and compare.
Starting point · simulation setup and result checking
Design space exploration
Parameter sweeps in my modelling projects are my starting point. I hope to learn how to choose and compare design parameters more systematically, beginning with simple examples and guidance on suitable optimisation methods.
Starting point · parameter sweeps
Hardware verification
I am interested in how hardware designs are checked. I would begin with the necessary digital-design and programming foundations, then learn to use simulation and verification tools on small examples.
Next step · foundations and small practice examples
My first-author memristor study trained me to derive operating constraints and compare model predictions with simulation. In the In₂O₃ study, I contributed validation, data curation and manuscript review. The LDO project added experience with team circuit verification. Together, these experiences motivate a move toward automated design exploration with explicit checks.
Evidence I bring
First authorModeling, simulation, analysis, and writing
A behavioral-level, pre-silicon study deriving analytical read-write constraints from the VTEAM state equation and evaluating them from device to neural-network scale.
The published study reports a 13.78x resistance window and 90.6% MNIST top-1 accuracy, with 96.08% Set-cycle energy reduction against its defined behavioral baseline.
Electronics 15(11), 2333 · Published 28 May 2026[paper][code][poster & research][publication certificate]
Journal: JCR Q2Engineering, Electrical & Electronic · 2025 JIF
Third authorValidation, data curation, and manuscript review
A two-dimensional numerical study of short-channel behavior and simulated DC/RF scaling across 20-700 nm top-gate In₂O₃ TFTs.
My credited roles were validation, data curation, and manuscript review and editing; the highlighted device and RF values are study-level numerical results.
Micromachines 17(5), 567 · Published 2 May 2026[paper][poster & research][publication certificate]
Journal: JCR Q2Instruments & Instrumentation · 2025 JIF
Published work is listed above. Ongoing research and team engineering projects are identified here with their current evidence and status.
I am developing a PSpice second-order memristor model that separates a retained conductance state from a relaxing history state, with a power-activated auxiliary state. Matched-x paired-pulse, selected 1T1R, STDP-like, and compact 2 × 2 simulations connect internal-state attribution to circuit-level behavior.
Simulation-only: 11.16% matched-x interval sensitivity versus 1.01% for the separately simulated history-off family; STDP-like ΔG = -1.82% to +1.09%; 24 compact-array read cases with no more than 0.450% unit-range state disturbance. The target denotes planned submission style only.
As a team member, I contributed to selected tasks across the competition stages: a 1.8 V CMOS LDO, eight simulation benches, a physical-verification trail, regional semi-discrete hardware, and national-stage automated-test preparation.
Read the LDO engineering case file
AI-generated conceptual overview, not the team's implementation schematic or measurement data. The LabVIEW interface illustrates national-final test preparation, not a completed or executable test system.
Selected team contributions under instructor guidance. CMOS work covers design and simulation; regional hardware is a separate semi-discrete LDO; automated testing remained preparation.
Team design & simulation
SMIC 180 nm transistor-level work covering a PMOS pass device, bandgap reference, folded-cascode error-amplifier path, feedback, bias, and compensation, followed by eight dedicated simulation benches.
Physical workflow
Top-level layout integration, Calibre DRC/LVS/PEX, and post-layout simulation. The detailed case file keeps the unresolved DRC results and line-regulation gap visible.
Team hardware task
BJT characterization and selection using TIP42C/TIP32C and BD139/BD135 candidates, followed by a 25 V-to-12 V semi-discrete LDO and regulation, stability, transient, and thermal evaluation.
Preparation only
IECUBE-3100/3839 and LabVIEW preparation for PWS/DIO/DMM control, voltage-accuracy, line/load-regulation and dropout scans, data logging, and result logic.
B.Eng. Candidate in Microelectronics Science and Engineering
College of Mechanical and Electrical Engineering
Weighted average: 89.43 / 100
Postgraduate recommendation (推免)Selected for the 2027 preliminary recommendation list
Academic transcript · English public copyStudent ID, gender, and online-verification QR removed. The official copy is available upon request.
Selected coursework: Semiconductor Device Physics, Circuit Theory, Analog and Digital Electronic Technology, Computer Principles and Architecture, EDA Technology and Application, Signals and Systems, and Large-Scale Integrated Circuit Design.
Semiconductor-device simulation, behavioral circuit modeling, MATLAB, and PSpice.
PVT, PSRR, and STB analysis; layout integration; Calibre DRC/LVS/PEX; post-layout evaluation.
Validation, data curation, reproducible analysis, technical writing, LaTeX, and public code sharing.
English: College English Test Band 6 (CET-6), 576.
Academic records · September 2026
Chinese and English transcripts, grading scale, weighted average, major ranking, enrolment and the CET-6 score report.
View all seven academic records
View certificate4 Aug 2026
第十届全国大学生集成电路创新创业大赛
Second Prize · National Final
View certificateDec 2024
第十六届全国大学生数学竞赛
First Prize · Non-Mathematics A
View certificateMar 2025
中南大学2023—2024学年优秀学生
2023–2024 academic year
Competition awards, scholarships and student honours.
View all award certificates · 获奖证明 ↗Fall 2027 PhD applications
I am preparing for doctoral research in AI for EDA, design space exploration and hardware verification. I would be glad to discuss how my microelectronics background, modelling studies and Codex-enabled simulation workflows could contribute to a research project.